A conventional probe apparatus includes a loader chamber 1 and a prober chamber 2 arranged adjacent to each other as shown in, e.g., FIG. 6. The loader chamber 1 includes a cassette receiving part for receiving a cassette containing a plurality of semiconductor wafers W therein, a wafer carrying mechanism for transferring the semiconductor wafers W taken out of the cassette one by one, and a pre-alignment mechanism for pre-aligning the semiconductor wafer W while transferring the semiconductor wafer W by the wafer carrying mechanism. The prober chamber 2 has a mounting table 3 which is movable in X, Y, Z and θ directions while mounting thereon a semiconductor wafer W, a probe card 4 having a plurality of probes 4A to be brought into electrical contact with electrode pads of devices formed on the semiconductor wafer W mounted on the mounting table 3, a fixing mechanism 5 for fixing the probe card 4 through a card holder (not shown), and a connecting ring 6 for electrically connecting the probe card 4 and a test head T.
The conventional probe apparatus is configured to inspect electrical characteristics of each of the devices by transmitting and receiving test signals between a tester (not shown) and the electrode pads of each of the devices formed on the semiconductor wafer W via the test head T, the connecting ring 6 and the probe card 4.
Further, in FIG. 6, reference numeral ‘7’ indicates an alignment mechanism for performing position-alignment of the semiconductor wafer W and the probe card 4 in cooperation with the mounting table 3; reference numerals ‘7A’ and ‘7B’ represent an upper camera and a lower camera, respectively; and reference numeral ‘8’ indicates a head plate to which the fixing mechanism 5 of the probe card 4 is attached.
Further, as illustrated in, e.g., FIG. 7, the mounting table 3 has a mounting table main body 3A, a mounting body 3B movable vertically with respect to the mounting table main body 3A, and a transfer mechanism for the semiconductor wafer W.
The transfer mechanism has through holes formed at three locations spaced apart from each other at regular intervals in a circumferential direction on the mounting body 3B and three elevating pins 3C movable vertically in the through holes. While the semiconductor wafer W is transferred by the wafer carrying mechanism 9, the three elevating pins 3C protrude upward from the mounting surface of the mounting body 3B to be in ready for receiving the semiconductor wafer W.
Next, the wafer carrying mechanism 9 is lowered, and the semiconductor wafer W is delivered to the three elevating pins 3C. Thereafter, the wafer carrying mechanism 9 is retreated from the mounting body 3B into the loader chamber 1. The three elevating pins 3C being received the semiconductor wafer W are lowered and retreated into the mounting body 3B and the semiconductor wafer W is mounted on the mounting body 3B. The semiconductor wafer W is held on the mounting surface of the mounting body 3B by vacuum adsorption. Next, the alignment mechanism 7 performs alignment of the semiconductor wafer W in cooperation with the mounting table 3, and the semiconductor wafer W on the mounting table 3 is brought into electrical contact with the probes 4A of the probe card 4, thereby inspecting electrical characteristics of the semiconductor wafer W.
However, in the conventional transfer mechanism for a semiconductor wafer W, the through holes which allow the elevating pins 3C to pass therethrough are formed at three locations, so that leakage of electromagnetic waves from the lower portions of the through holes toward the semiconductor wafer W can be occurred. This causes electrical noise during inspection of devices formed on the semiconductor wafer W, which may adversely affect the inspection result. Further, in the case that devices generate heat, the semiconductor wafer W can be cooled to a predetermined inspection temperature by a temperature control mechanism provided at the mounting table 3. However, it is not possible to cool down devices formed at portions corresponding to the three through holes. Accordingly, heat spots may be generated, and the inspection may not be performed at the required inspection temperature. Moreover, in the case of devices to be inspected by applying a high voltage, abnormal discharge may occur in the through holes during the inspection.
The above-described elevating pins have been widely used conventionally. For example, elevating pins described in Japanese Patent Laid-open Application No. 2002-64132 and correspond U.S. Pat. No. 6,739,208 are different from those shown in FIG. 7 in that they are used to transfer a curved semiconductor wafer. These elevating pins are made to project upward from the mounting table with different projection amounts to incline the curved semiconductor wafer. This makes is possible to reliably transfer the semiconductor wafer W between the wafer carrying mechanism and the mounting table. In addition, elevating pins described in Japanese Patent Laid-open Application No. 2007-288101 are substantially the same as those illustrated in FIG. 7 which are widely used in general.